Designing I/O modules for SUMIT

PC/104 and Small Form Factors — October 23, 2009

6While we've had several looks at Stackable Unified Module Interconnect Technology (SUMIT), we wanted to see a more hands-on example of designing an I/O board using the concepts in the specification. Qi walks us through the thinking behind such a design.

SUMIT provides a flexible combination of high-speed serial buses and legacy I/O support for enabling powerful embedded I/O module designs in small form factors. Examining methods such as lane shifting, which pertains to PCI Express (PCIe) lanes as well as USB, can simplify the process of designing with the new SUMIT specification for embedded I/O modules.

The following discussion will introduce SUMIT and its underlying concepts, then describe an example of a real-world SUMIT design featuring the latest high-speed PCIe and USB interconnects as well as an ISA bus bridge and legacy serial ports, which are still widely used in industrial, medical, and military applications.

Introduction to SUMIT

SUMIT is a stackable expansion connector specification targeted for new products including state-of-the-art serial buses and legacy chipset expansion buses all in the same form factor. The specification is an I/O-centric approach defining the connector and stacking method, but is independent of the stacked board form factors. Figure 1 shows SUMIT’s basic structure and summarizes the buses, interfaces, and signals carried.

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Figure 1: SUMIT’s two connectors carry signals for modern and legacy interfaces.

Two connectors are used on each expansion module, SUMIT A and SUMIT B. These connectors carry multiple high-speed serial PCIe and USB 2.0 buses and include Low Pin Count (LPC), Serial Peripheral Interface (SPI), and SMBus/I2C for legacy requirements. While the SUMIT B connector carries mostly PCIe interfaces, the SUMIT A connector carries a single x1 PCIe and four USB 2.0 buses, as well as the legacy interfaces.

Each SUMIT module generally has an upper and lower SUMIT A and an upper and lower SUMIT B. Some lower-cost modules only require SUMIT A, which is accommodated for in the specification. The optional SUMIT B connector is used in most module implementations. SUMIT defines the alignment and separation of the two SUMIT A and SUMIT B connectors, but not the size of the module. This flexibility allows boards that follow the SUMIT specification to be connected together easily, even if the board form factors differ.

SUMIT uses two high-speed, fine-pitch (0.635 mm) stacking connectors with a central ground blade that provides impedance control for transferring high-speed serial buses between modules. Different stacking heights are available for use when additional clearance between modules is required. For bulky components on the module, the standard stack heights are 15.24 mm and 22 mm.

Figure 2 shows a stacked SUMIT system comprising a lower board, an Ampro by ADLINK CoreModule 730, and an upper board, an Ampro by ADLINK MiniModule SIO. The two SUMIT connectors can be seen on the top side of the top module on the board edge at the forefront of the picture. Note that in this case, the two boards have differing form factors, and the connectors are relatively small even though they are transferring several high-speed buses between the two modules.

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Figure 2: A stacked SUMIT system can transfer high-speed buses between boards with differing form factors.

PCIe implementation in SUMIT

As mentioned earlier, SUMIT carries multiple PCIe interfaces on both connectors. The SUMIT B connector has x1 and x4 lane PCIe links that can be used together or as individual lanes. In contrast, the SUMIT A connector has a single x1 lane PCIe link.

One of SUMIT’s significant features is its PCIe link-shifting method, which facilitates straightforward link distribution to the modules in the stack. Link shifting allows multiple boards to be stacked while avoiding configuration jumpers or switches to set up the PCIe routing. The method also enables optimal board layout for passing high-speed signal buses from board to board up the stack.

To aid understanding of this method, Figure 3 shows link shifting in a generic, simplified form for three stacked boards: X, Y, and Z, with four links originating on baseboard X. Each board uses one link internally from the four passed up from below, and then passes the remaining links up to the board above, but shifts all the remaining links to the left, as shown in Figure 3. This shift accounts for the link that is used internally and not transferred to the board above.

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Figure 3: Link shifting provides an efficient method for passing links from board to board up the stack.

For example, board Y uses Link 1 internally and passes the three remaining links up to board Z, which uses Link 2 internally. However, board Z does not need to be reconfigured to account for its position above board Y because it always receives the link it uses internally from the leftmost side of the set of links.

This approach allows multiple boards to be stacked without requiring any hardware configuration to indicate which links should be used on a particular board. Each module in the stack uses the links starting at the left side. Obviously, the modules cannot use more links than what the base module provides; however, using this shift method, link distribution between modules occurs naturally as a result of stacking. By shifting links over small distances between connector pins, this approach enables efficient PCB layout, which is important to maintain signal integrity for the high-speed PCIe buses used.

Figure 4 depicts the PCIe link-shifting method used in the SUMIT specification. Because the PCIe lanes are distributed over both SUMIT A and SUMIT B, links are also shifted between these two connectors. The x1 link from SUMIT B gets shifted to SUMIT A, and the first link of the x4 gets shifted to the x1 link on SUMIT B.

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Figure 4: As applied in SUMIT, the PCIe link-shifting method distributes links between the SUMIT A and SUMIT B connectors.

Note that a board using the x4 links on SUMIT B (but neither of the x1 links) should be the second board up in the stack so that the x4 bus is not then transferred upwards. In that case, the x1 links on SUMIT A and B are passed straight up through the board with no shift. A shift is not needed if a link is not used internally in the board. When link-shifting occurs, the link clocks are shifted along with the data signals to ensure they stay matched together.

USB, LPC, I2C, SPI, and MiniBlade in SUMIT

SUMIT defines four USB 2.0 interconnects. Similar to the PCIe link-shifting method, USB interconnects are shifted between module connector A pins. For example, if a module at the base of the stack uses the USB-0 interconnect on SUMIT A, it passes up the remaining three USB interconnects to any modules stacked above. This bus-shift method allows the four available USB buses to be distributed to the modules in the stack without requiring any extra module configuration. The same PCB layout benefits that can be achieved by transferring PCIe links from board to board apply to USB interconnects as well.

The LPC bus is included in the SUMIT specification to allow a wide range of legacy interfaces to be used within the SUMIT stack. LPC capabilities complement those available on the high-speed PCIe and USB interfaces, providing maximum flexibility for implementing user applications while maintaining high-speed buses on the SUMIT stack.

I2C and SPI are widely used medium-speed serial interfaces that are included in the SUMIT specification for connecting to devices that use these buses. The SPI bus in particular is becoming a popular addition in many chipset designs.

MiniBlade is a new storage specification that uses USB and PCIe interfaces and naturally fits into the SUMIT implementation because both interfaces are available on the connector stack. This ruggedized storage form factor can withstand significant exposure to shock and vibration.

MiniModule SIO example

Figure 5 portrays the MiniModule SIO, illustrating how the aforementioned features can be implemented in a real-world application example of SUMIT.

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Figure 5: The MiniModule SIO implements SUMIT’s lane-shifting methods.

The SUMIT A connector on this module contains a MiniBlade interface that uses one USB interconnect and one PCIe link. Two additional USB interconnects are brought to a header for external use.

Because the remaining USB interconnect is not used on the module, it is transferred to the upper module connector, allowing the next stacked board above the MiniModule SIO to use the USB 2.0 interconnect for the application.

The MiniModule SIO uses the LPC to implement a whole set of legacy I/O interfaces, including a full ISA bus on PC/104 connectors. This uses the SUMIT LPC bus to interface to an LPC-to-ISA bridge, enabling SUMIT to easily support PC/104. An SMSC 3114 SIO is included to provide rugged I/O capability including quad serial RS-232/422/485 interfaces on dual DB-style connector interfaces and dual header interfaces, along with a keyboard and mouse interface and a legacy parallel port on a header.

Because this module uses one PCIe link in the MiniBlade interface, the remaining PCIe links are shifted. So SUMIT B x1 PCIe is transferred through a link shift to SUMIT A x1.

Although the x4 PCIe is not shown in this diagram because of the link shift of the x1 PCIe from SUMIT B to SUMIT A, the x4 PCI is also link shifted in SUMIT B, but only when it is used as 4 PCIe x1. The SPI bus is not used in this module, so it is simply transferred through this module from the lower board to the board above on the SUMIT A connectors.

Interfacing without reconfiguration

SUMIT is a flexible and powerful specification for interfacing stacked modules. The MiniModule SIO provides an example of a recently developed board that implements most of the features of the SUMIT specification and combines slow legacy interfaces with state-of-the-art high-speed interfaces such as PCIe and USB.

With no hardware configuration needed to route multiple interfaces, SUMIT gives designers a solution for creating embedded expansion modules that require high-speed interfaces as well as legacy support.

Qi Chen is the senior director of engineering for Ampro ADLINK Technology, with U.S. headquarters in San Jose, California. She has 20 years of industrial experience working in a wide range of technical and management roles for industry-leading technology companies in the United Kingdom and United States. Qi previously worked as the general manager for the U.S. division of a global video surveillance company. She obtained her degree in Electronics in Shanghai and worked for five years at the Shanghai Standards Institute before studying at the University of Leeds, where she received her PhD in Electronics.

Ampro ADLINK Technology 408-360-4367 qchen@adlinktech.com www.adlinktech.com