The PC/104 Embedded Consortium's PCI/104-Express and PCIe/104 specifications preserve the integrity of the PC/104 architecture while integrating the latest in high-speed bus technology. A newly proposed addition to PCIe/104 promises increased signaling functionality and flexibility in stacking PC/104 designs.
Developed by the PC/104 Embedded Consortium and adopted by member vote in March 2008, the PCI/104-Express and PCIe/104 specifications established standards for using high-speed PCI Express (PCIe) in embedded applications. The PC/104 Consortium chose PCIe because of its desktop/laptop market adoption, performance, scalability, and growing silicon availability worldwide. The bus provides a high-performance physical interface while retaining software compatibility with existing PCI infrastructure. Incorporating PCIe within the PC/104 architecture provides many advantages in embedded applications, including fast data transfer, low cost due to PC/104’s unique self-stacking bus, high reliability due to PC/104’s inherent ruggedness, and long-term sustainability.
PCIe/104 is implemented by a pair of high-speed surface-mount connectors, which is a major change from the through-board stacking connectors used by PC/104 and PCI-104, opening new possibilities for host board manufacturers. The connector on top of the host is not required to be electrically connected to the connector on the bottom of the host. That means a design can have a PCIe/104 bus going up and a completely separate PCIe/104 bus going down, creating a total of eight PCIe x1 links, two PCIe x16 links, and four USB ports, thus doubling the number of peripheral boards that can be supported. Furthermore, because the specification requires peripheral boards to be universal, all existing peripheral boards will work either above or below the CPU.
This begs the question: Can there be a different bus on one side? The answer is yes, but which bus? An additional bus would be beneficial if:
· Many existing peripheral cards worked on either bus
· Peripheral card manufacturers would only have to build one version of a card to work on any host
· No damage would result from cards being accidentally stacked and powered incorrectly
· There were simple rules for system configuration
Type 2 bus proposal
During the Consortium’s development of the PCI/104-Express specification, a debate arose regarding which signals to include on the bus. A x16 PCIe link uses lots of connector pins that can be used for things like SATA, USB, and Low Pin Count (LPC) bus if the application does not require the bandwidth provided by the fat pipe. If this is engineered correctly, functionality can be added without making the specification overly complicated and causing confusion in the marketplace.
In the PCIe/104 bus depicted in Figure 1, Bank 1 contains four PCIe x1 links, two USB 2.0 ports, SMBus, and some control signals. Bank 2 and Bank 3 contain only the PCIe x16 link. If Bank 1 is completely maintained, along with the same power, ground, and control signals, the bus will not conflict with any existing PCIe x1 or USB peripheral card. These cards will stack all of the unused PCIe x16 pins directly through the board.
If the x16 link is changed, the PCIe x16 cards will be the only peripheral cards affected, providing lots of pins for a new bus. Note that Bank 2 has PCIe transmit signals and Bank 3 has PCIe receive signals. This convention, as well as all power and ground pins, must be maintained to ensure that improper stacking does not cause destructive consequences.
In addition to the four PCIe x1 and two USB 2.0 ports, the bus should include signals typically found on a processors and chipsets from any of the major processor companies. Two SATA ports facilitate hard drives in the PC/104 stack, while two USB 3.0 ports cater to the future. Lane shifting on the SATA and USB 3.0 means peripheral boards will continue to be universal. SATA and USB 3.0 are high-speed signals that require a connector with good signal integrity, such as the Samtec Q2 series used on PCIe/104. LPC adds support for legacy devices, and many applications need a battery to back up the real-time clock. This still leaves room for two PCIe x4 links that are compatible with PCIe/104. Table 1 shows the complementary nature of this selection.
All peripheral boards that use a PCIe x1 link, PCIe x4 link, or USB 2.0 link on a PCIe/104 bus will work on a Type 2 bus without any changes to existing peripherals. This allows peripheral module manufacturers to create one board that works on either bus and gives users confidence that the board will be interoperable with other boards.
Because designers can mechanically and electrically plug into either pinout configuration, it is important that neither board will be damaged if this inadvertently happens. The bus is designed with the same power/ground connections and similar transmit/receive connections and will hold the host processor in reset if incorrectly connected.
Stacking configurations and usage rules
Host processors can have both connector pinout configurations on one board for additional functionality. For example, a design with PCIe/104 on the bottom and Type 2 on top will support a bottom-up stack configuration that includes the power supply, PCIe x16 video card, CPU, and SATA hard drive. To create a compact, expandable SBC design where x16 PCIe is not required but the additional functionality of SATA, USB 3.0, and LPC is, a host can use Type 2 on the top and bottom. This can be a useful configuration for embedded processors such as Intel’s Atom. Just like PCIe/104, Type 2 provides mechanical backward compatibility and bridging to PCI-104, PC/104-Plus, and PC/104 modules (see Figure 2).
With a simple naming convention such as Type 1 and Type 2, designers can easily create and understand usage rules:
· Any PCIe x1, PCIe x4, or USB 2.0 peripheral is universal and can plug into either Type 1 or Type 2. This covers most peripheral boards.
· All PCIe x16 peripherals must plug into Type 1.
· All SATA, USB 3.0, and LPC peripherals must plug into Type 2.
· Anything plugged into the wrong bus holds the system in reset and causes no damage.
PCI/104-Express and PCIe/104 are solid specifications that provide a path to the future while maintaining compatibility with the past. Any additions to the specifications must be easy to use and understand, integrate important features without breaking existing boards, and not cause confusion in the marketplace. Additions must be complementary to, not competitive with, the existing specifications. RTD’s PCIe/104 Type 2 proposal meets all of these requirements and is now in production.
Jim Blazer is Vice Chairman and CTO of RTD Embedded Technologies, where he is responsible for managing intelligent data acquisition systems and embedded PC designs. Jim currently serves as president of the PC/104 Consortium and holds a BSEE from Penn State University.