COMs embrace next-gen interfaces
To extend lifetime in the market, COMs need a generous helping of signal bandwidth headroom and reserved pins.
Just when it seemed safe to design the latest low-power COM Express or Qseven COM, a wave of higher-bandwidth interfaces looms just around the corner. Upcoming PCI Express, USB, network, disk, and video speeds pose a challenge to today's COM pinouts and connectors. For COMs to stand the test of time, they must evolve to address broader market requirements.
Unlike SBCs, which bring chipset I/O to a variety of connectors on the board, Computers-On-Modules (COMs) with few exceptions are constrained to route all bus and I/O signals through their standardized baseboard interface connectors. Consequently, evolving bus speeds and I/O interfaces tend to expose electrical limits and weaknesses of a COM standard’s baseboard interface connector scheme, while completely new buses or I/O interfaces are unlikely to be supported within the baseboard connector’s signal definitions.
As a result, unless their baseboard connector interfaces are endowed with a generous helping of signal bandwidth headroom and reserved pins, COM standards won’t survive long in the market, given that bus and I/O interface technologies are a fast-moving target. These I/O interface innovations abound, with speeds and densities doubling every year or two as if governed by Moore’s Law. For example:
· PCI Express (PCIe) 2.0 and 3.0 comprise higher-frequency signals – 5 GHz and 8 GHz, respectively – than the 2.5 GHz PCIe 1.0 standard.
· USB 3.0 increases the number of data lines from two to six (one differential pair to three). USB 3.0 is backward-compatible with USB 2.0 when the original differential pair is connected.
· Video has already evolved from analog VGA to TTL digital LCD, to LVDS differential pair LCD, and to SDVO, and will soon move to DisplayPort. SDVO allows flexible conversion of digital video to analog VGA, DVI, TV-out, and other types of formats.
· Now that Parallel ATA (PATA, aka IDE) has mostly vanished from chipsets, Serial ATA (SATA) is rapidly climbing through 150, 300, and 600 Mbps speeds for rotating disk drives and solid-state disks.
· GbE is part of all current COM definitions, although companies take differing approaches to incorporating it. While most COMs include both the MAC and PHY (usually copper) layers, an emerging method brings the digital media-independent interface off the module to give the baseboard the choice of a copper or optical PHY.
In most cases, these upcoming faster signals exceed the capabilities of the baseboard interfaces on existing COM standards. Similarly, the modules’ standardized baseboard interface signal pinouts do not typically support the incorporation of new I/O interface definitions that may be desired in the future.
Vive la diff pair différence
To achieve higher data throughput, high-speed serial interfaces implement low-voltage differential pair (diff pair) routing topologies. The traces must adhere to strict routing rules including matched (equal) trace lengths, widths, and spacing within very tight tolerance and few allowed feedthroughs (vias) for changing board layers.
These days, module and baseboard designers need to supplement their digital design skills with an RF perspective. The single-ended and differential transmission line (T-line) impedances (Z0=√L/C) are specified within narrow ranges, imposing challenging constraints on trace widths and circuit board stack-up thicknesses. With limited space on COMs, it can be challenging to reduce outer (microstrip) traces or to raise inner layer (strip line) traces to reach the single-ended 50 ohm or 60 ohm requirements.
The COM’s baseboard interface connectors impose impedance discontinuities (changes in Z0) leading to signal reflections, as well as insertion loss (near end), return loss (far end), and crosstalk (near end and far end). Spice models can simulate T-line performance, while network analyzers (frequency domain) and signal analyzers (time domain) can characterize connectors and create eye diagrams. To achieve true PCIe 2.0 or 3.0, USB 3.0, SATA 300, or GbE compliance, the rising and falling edges must remain fast enough to stay outside of the eye.
Each PCIe lane comprises a transmit diff pair (Tx+ and Tx-) moving away from the chipset and a receive diff pair (Rx+ and Rx-) coming to the chipset from the baseboard’s target device. The target device (a commercial IC or an FPGA, for example) contains a SERDES PHY.
For PCIe 1.0, many targets can use the chipset’s transmit diff pair to generate their own internal timing. Some extra latency can result from the chipset data to the data provided back to the COM by the baseboard target. However, PCIe 2.0 devices typically must have a separate clock diff pair (CLK+ and CLK-) to generate the return timing properly. As diff pair signals cannot be bussed or shared among multiple target devices, baseboards with multiple PCIe 2.0 devices must buffer multiple copies of the clock when used with COMs like COM Express, which only provide one clock diff pair. However, buffering the clock introduces undesirable jitter. Newer standards like COM Interconnect Technology (COMIT) address this shortcoming by providing multiple clock diff pairs to the baseboard.
So the real question is: What’s happening in the COM market to prepare for next-generation bus and interface advancements?
ETX, the first de facto x86 COM standard, was launched 10 years ago. While serial ports, dual IDE channels, and the ISA bus were included in chipsets at that time, those interfaces are no longer included in current chipsets and therefore require additional chips. Similarly, 10/100 Ethernet controllers are starting to reach end-of-life status now that Gigabit controllers are prevalent. Given these migrations, ETX and its PCIe-enriched XTX spin-off can be expected to fade from the market in the next 5-10 years.
COM Express, designed to handle up to 188 W of power through its 440-pin dual-connector interface, is a popular choice for modules based on high-end multicore processors such as Intel Core Duo and Core i7. Since it was defined six years ago for the Pentium M processor and 915 chipset platform, COM Express could not anticipate the completely different chipset bus and I/O content of Intel’s two Atom roadmaps; consequently, many Atom-optimized standards such as Qseven, COMIT, and CoreExpress (Figure 1) have emerged to fill the void. These new standards are aimed at reducing the size, weight, and power of COM and baseboard assemblies.
Qseven uses the lowest-cost connector scheme – the MXM mobile graphics module connector first popularized by NVIDIA. The COM’s gold-plated fingers plug into the memory-style connector in a manner reminiscent of the old DIMM PCs. However, the MXM connector is limited to PCIe 1.0 and USB 2.0 signal frequencies (though a faster version is reportedly in the works).
Two newcomers under the auspices of the SFF-SIG – COMIT and CoreExpress – can accommodate the higher speeds and new signals of several next-generation I/O interfaces. COMIT, for example, utilizes a connector system claimed to be capable of diff-pair signaling at up to 9 GHz bandwidth – enough to allow a future COMIT revision to support PCIe 2.0 and USB 3.0. CoreExpress, meanwhile, adds forward-looking modifications like DisplayPort as an alternate video definition in the SFF-SIG’s approved version. Additionally, CoreExpress uses the same 220-pin board-to-board connector as COM Express (one instead of two per module), which is said to provide reliable operation up to 6 GHz.
Seeking market verticals
Another trend in COM evolution is a diversification of feature sets. Until recently, COMs in the x86 world were limited to implementing relatively generic embedded PC functionality based on various combinations of desktop or mobile PC CPUs, chipsets, and I/O interfaces from manufactures like Intel, AMD, and VIA Technologies. While maintaining reasonably consistent COM feature sets, the flip side of this tendency was to commoditize the COM market, shrink profit margins, and squeeze out smaller and potentially more innovative vendors.
Today, manufacturers are going beyond the minimal embedded PC call of duty to preintegrate silicon and drivers targeting specific markets and applications in an effort to differentiate COM offerings and quicken OEM time to market.
CoreExpress represents one of the first such open-standard, application-oriented x86 COMs through its inclusion of a Controller Area Network (CAN) interface, a popular bus in automotive, military, and industrial applications, baked into its baseboard interface. The module’s ability to use copper or optical PHY on the baseboard also offers an advantage over other COMs for communication applications. At 58 mm x 65 mm, it is one of the smallest COMs currently available and the only all-digital x86 standard COM.
COMIT is also expected to address vertical market requirements (see sidebar). Its baseboard interface definition includes a substantial number of reserved that await assignment by the SFF-SIG’s COMIT working group, which has invited new members to join in the effort of tuning COMIT to the needs of the markets and applications they serve.
COMIT’s application flexibility
Unlike COM standards such as Qseven or CoreExpress, the COMIT specification is limited to defining a baseboard interface connector along with its set of bus signals. This leaves the specification of the form factor as an exercise for the manufacturer, allowing the vendor to address the requirements of specific markets and applications. For example, the first COMIT COM from WinSystems measures 62 mm x 75 mm and is intended for use as a processing core on standard SBC form factors such as EBX, EPIC, and ECX.
The COMIT baseboard interface consists of a 6 x 40-pin array with a unique zipper-style connector insertion claimed to offer high reliability in ruggedized applications (see Figure 2). Based on Samtec’s SEARAY connector system, the interface supports differential pair signaling rates up to 9 GHz and is usable with next-generation high-speed serial interfaces like PCIe 2.0 and USB 3.0.
Giving COMs an extra lease on life
New COM standards and updates to existing standards are released every year to keep pace with advancing bus and interface technologies, which continually increase in speed and diversity. Although several life-extending updates typically occur within the lifespan of a COM standard, baseboard pinouts and connector designs ultimately conspire to limit a COM standard’s useful life.
For these reasons, new COM standards like the SFF-SIG’s COMIT and CoreExpress specifications must be designed with baseboard interface schemes that provide a healthy measure of unused signal bandwidth headroom and reserved pins to lengthen the COM’s time in market.
Colin McCracken is VP of marketing at Diamond Systems Corporation. He has more than 20 years of experience in the embedded systems market in various marketing and engineering capacities, most recently at ADLINK Technology and previously at Ampro Computers. Colin is also a board member of the SFF-SIG (www.sff-sig.org), which he cofounded in 2007.