Cool power sensation

Sensor platforms are proliferating around the edges of the network in both the civilian and the military spheres. For examples, think of the remote devices on buses, trucks, and oil rigs that are monitored via the Internet of Things (IoT) or the unmanned surveillance nodes in the network-centered warfare infrastructure. To be effective, these "edge" devices need to be as self-sufficient as possible, not just in processing capability but also in energy use.

Size, weight, and power (SWaP) has long been the mantra for embedded electronics. Every military platform, from the humblest handheld device or miniature unmanned vehicle to the largest weapon system must face these constraints at some level. For battery-dependent devices, energy efficiency is a more urgent concern. The smaller the platform, the bigger the bite from power-hungry computers.

Although it’s sometimes overlooked, a key driver behind SWaP and system power concerns is chip-level performance per watt. Today’s advanced semiconductors, sporting billions of transistors, can burn a lot of power and dissipate a lot of heat. A major challenge for overall power budgets is constraining chip requirements within the tightest possible limits.

In the sensor-processing realm, much has been done with field-programmable gate arrays (), chips that can be optimized not only for speed but also for power management. These devices’ one-of-a-kind firmware is expensive to create, however, and can be equally costly to upgrade. Therefore, military customers often express a preference for general programmable processors that can use open source software like . Conventional CPUs, which fill the “general” bill, just can’t compete in performance with FPGAs, though.

This dilemma has created an opening for general-purpose graphics processing units (GPGPUs). Originally developed for the gaming market, these hybrid chips are designed for efficiency and have improved in power performance. They feature hundreds of parallelizable processing units, or cores, as well as multiple CPUs. Fortunately, GPGPUs have proved to be adaptable to the military market. These software-programmable chips are able to process oceans of image data in a timely fashion, compress it, and transmit it to decisionmakers within tactical deadlines.

The latest GPGPU in NVIDIA’s low-power Tegra system-on-chip (SoC) product line, the Tegra X1, provides a teraflop of compute performance (1 trillion floating-point operations per second) at a power cost of only 10-12 watts.

That’s almost three times the raw performance of the company’s predecessor chip, the Tegra K1, which delivers 326 gigaflops at a fractionally higher power output, or about twice the performance per watt of the predecessor chip’s GPU function. That’s in spite of the fact that the X1 has 256 GPU CUDA cores and eight CPU cores compared with the K1’s 192 CUDA GPU cores and four CPU cores. (CUDA, which stands for Compute Unified Device Architecture, is NVIDIA’s GPU programming model.)

Some of the reasons for this performance-per-watt improvement are the X1’s smaller process size (20 nm vs. 28 nm), more efficient memory technology, and enhanced power management features compared with the K1.

The X1 is likely to be attractive to military users, since it can be plugged into existing K1 boards as a more or less seamless upgrade to run K1 applications, only faster.

An example of a minimal-footprint GPGPU product is the mCOM10-K1, a ruggedized, extended-temperature, credit card-sized K1 module that is upgradeable to an X1 configuration. (Figure 1.)

The benefits from improved performance per watt will be significant, especially as the new technology is backwards-compatible. For one thing, it will be possible to fuse higher-resolution sensor data, using more input devices simultaneously. Additionally, new applications such as neural net-based automatic target recognition and autonomous navigation and mapping will become more plausible. The excess compute capacity in these new chip sets might even be sufficient to meet all the processing needs of small robotic vehicles. I

Charlotte Adams writes extensively on microelectronics, avionics, software, embedded computing, and other developments for a number of military and aerospace publications. She worked for the U.S. Library of Congress for several years, after which her career took her into journalism; she served as editor of Avionics magazine. Charlotte received an honors degree in English Literature from Duke University.

Figure 1: The Abaco Systems mCOM10K1 Type 10 Mini Module gives designers 326 gigaflops of performance while consuming minimal power.