PC/104 architecture: Solid

Evaluation of the challenges of the embedded marketplace is a never-ending saga. Each technology has its benefits and drawbacks, and each feeds the ideas of tomorrow. Throughout its history, the PC/104 Consortium has taken the approach of stressing the characteristics of stability, evolution, backward compatibility, interoperability, maintainability, and upgradability for its PC/104 architecture. These characteristics have enabled its long-term survivability and have provided embedded developers and end users a mechanism to maximize product lifecycle investments and reductions in costs.

The PC/104 specifications begin by focusing on the evaluation of mainstream bus architectures for their soundness and acceptance in the marketplace. This provides a solid foundation from which everything else can evolve. Testaments to the effectiveness of this approach are the PC/104 stackable ISA and PCI-104 stackable PCI buses, which have proven themselves for over 20 years in the harshest of conditions, leading to their vast adoption.

But as the computer industry accelerated in its advancements, so did the complexity and choice of bus architectures, making the creation of next-generation stackable specifications that much harder. As high-speed, low-voltage differential serial interfaces came onto the market, new challenges emerged for PCB and connector construction that had to be addressed for future evolution. This evolution came quickly with refinements to transfer rates, protocols, and encoding schemes, leading to PCI Express alone seeing a move from Gen 1 (2.5 GTps) to Gen 2 (5 GTps) to Gen 3 (8 GTps) in 2003, 2007, and 2010, respectively. And so too did the speeds of USB and SATA increase.

Therefore, the Consortium chose for its PCIe/104 specification a high quality, surface mount connector with signal bandwidth headroom and mechanical properties that were specifically developed to account for standoff tolerances and provide large connector-to-connector wipe. It was also developed with ruggedness in mind for products that might be exposed to the entire spectrum of environmental conditions, from the static in ambient temperatures to the worst shock and vibration in extreme temperatures. And this choice has paid off since, as this is being written, a new revision of the PCIe/104 specification that incorporates the ability to run PCI Express Gen 2 and 3 is being released to Consortium members for a vote. If adopted, this capability provides two benefits: overall increased bus bandwidth and potential reductions in the number of high-speed serial links needed to connect to a peripheral card functionality since more data can be transferred for a given link number.

The surface mount characteristics of the stackable PCIe/104 connector also allow the top and bottom side connectors to be electrically detached if the board developer so desires. This feature can expand the potential capabilities of the stack by allowing simultaneous up and down stacking, doubling of the number of available bus links, and having different bus configurations, such as Type 1 going down and Type 2 going up. The choices are limited as a function of the processor of choice, PCI Express switches involved, or bandwidth sharing incorporated. And since the connector is surface mount, one can even eliminate the top or bottom connector on a host if stacking in one direction is desired, thereby realizing additional usable PCB real estate. Compound this with the universal configuration of each functionality found on the PCIe/104 connector, and versatility, compatibility, and interchangeability of the specification are maximized.

By paying close attention to optimizing backward compatibility with their other specifications, the PC/104 Consortium provides paths to evolving mainstream bus architectures while allowing users to continue leveraging past investments (Figure 1). This helps minimize software changes, mechanical system modifications, and recertification requirements. And these standards will remain viable as long as processor manufactures, FPGA IP cores, and peripheral device vendors continue to support the embedded market. This is what gives all of the Consortium’s specifications lasting power, and why there are so many products available using stackable PCI Express, PCI, and ISA busses today.

Figure 1: PCIe/104 provides paths to evolving mainstream bus architectures while allowing users to continue leveraging past investments.
(Click graphic to zoom)

The versatile family of complementary, stackable specifications based on the PC/104 architecture has been providing long-term solutions for a vast array of applications for more than 20 years, and is still finding itself in new areas every day.

For more information visit the PC/104 Consortium website at www.pc104.org.