PC/104 architecture maintains relevance in a competitive field

PC/104 is into its third decade, standing the test of time, while myriad form factors of yesteryear have faded into irrelevance. So why is PC/104 so persistent? How has it survived? The simple answer for me is the tireless work of the consortium that lies behind its continued success. A collaboration of companies with a common vision, it was formed in 1992 with 12 members but now has almost triple that. The PC/104 Consortium ensures PC/104’s continued relevance. The spine of a PC/104 stack is the desktop-derived peripheral bus, arguably the key evolution since 1992 (Figure 1).

Figure 1: WinSystems’ PCM-VDX-2-512-ST is a fanless PC/104 board with the desktop-derived peripheral bus.

The PC/104 Consortium’s continued role is to revise and evolve the form factor to encompass the next generation of peripheral bus, from a (now relatively) low 4.77 MHz ISA bus to the 8 GHz that’s available today. The consortium recognizes the importance of backwards compatibility and longevity. Therefore, new revisions of the spec optionally retain the previous generation of peripheral bus to satisfy innumerable legacy PC/104 applications.

The form factor’s unique selling point is of course its stackability, a trait that it has exclusively retained while the remaining vast infrastructure of embedded and desktop computing solutions continue to rely on a traditional backplane format. The benefit of stacking is functional scalability: the ability to expand or contract functionality, to facilitate in-situ upgrades of legacy installations, or offer a range of configurations effortlessly from a single base product.

The evolution of PC/104 is analogous to that of the ubiquitous Ford Mustang. The old adage “if it ain’t broke, don’t fix it” applies to both in the retention of their original unadulterated purity, and it’s under the hood where technology has kept both at the forefront of their respective industries – PC/104’s new engine is PCI Express (known as PCIe).

PCIe integration into PC/104

The PCIe/104 and PCI/104-Express specifications were formally adopted by PC/104 Consortium voting members in 2008, with the former exclusively providing the PCIe peripheral bus and the latter also retaining the previous-generation PCI bus for its famed legacy support. Revisions to larger-footprint standard form factors meant that EPIC-Express and EBX-Express, while not supporting a stackthrough architecture, represent valid baseboards to suitably support a rising PCIe/104 peripheral stack (Figure 2).

Figure 2: EPIC-Express and EBX-Express revised to support a rising PCIe/104 peripheral stack.

PCIe/104 satisfies the breadth of I/O diversity required without falling into the incompatibility trap that system-on-module (SoM) form factors invariably experience due to multiplexed pin assignments. PCIe/104 offers two distinct types of fixed I/O configurations that offer flexibility without sacrificing PC/104’s scalable compatibility (Table 1). Type 1 offers a high-speed 1x16 or 2x8 PCIe link, providing 8 Gbps peripheral bus bandwidth for the intensive (invariably video) processing applications.

Where such bandwidth isn’t needed, Type 2 trades this for dual USB 3.0, SATA, x4 PCIe links, and a low-pin-count (LPC) bus. Such a diverse range of possible stack configurations is underpinned by the bus’s mechanical flexibility and built-in electronic dynamic compatibility. The flexibility and expandability of the bus and its mechanical layout allow different stack configurations to support an array of diverse project requirements. Intelligent Link Shifting automatically assigns PCIe links throughout the stack while a PCIe/104-to-PCI bridge peripheral board adds legacy PCI support where the choice of CPU module cannot.

The PCIe advantage

Due to the computing industry’s obsession with backplane motherboard and slot daughterboard methodology, PC/104 finds itself as the only nonbackplane system supporting a PCIe peripheral bus. This reality translates to PC/104 being the only format that lets designers evolve existing solutions to include functionality not envisioned, or technology that didn’t even exist, during the initial design phase.

The evolution of USB to version USB 3.0 has provided unprecedented bandwidth to hot-swappable peripheral devices evolving in parallel with the fixed PCIe bus to which it is effectively a subset. The ubiquitous adoption of both has driven costs so low today and their respective capabilities and pricing structure are so similar that they invariably go hand-in-hand, complementing each other to satisfy either fixed or removable peripheral devices. Such is the design of PCIe that a single high-speed x16 bus can be split to provide double the lanes at half the bandwidth, and so on.

The first beneficiaries of a new, higher-bandwidth peripheral bus are invariably graphics cards, always the first to push the bus-bandwidth boundaries and arguably the key driver in the commercial-computing arena when next-generation products get developed. In the embedded space – with ever-increasing die density and exponential improvements in integrated graphics chip sets – increasingly the traditional peripheral boards find themselves locally satisfied within a system-on-chip (SoC). This coverage negates the need for such peripheral bus bandwidth. Additionally, embedded-computing technology naturally strives for miniaturization.

The real-estate pressure of often redundant, large peripheral bus connectors in a design that doesn’t fully utilize them poses a miniaturization bottleneck. One solution to this problem is OneBank. The PCIe/104 and PCI/104-Express specification defines three identical and adjacent connectors, integrated into one three-way connector. OneBank replaces that bank of three (superfluous in the majority of small-form-factor applications) with one connector that is identical to the first bank of both Type 1 and Type 2 PCIe/104 connectors. Maintaining the location of the first bank ensures compatibility with existing PCIe/104 boards as well as one another. Offering a 60 percent reduction in connector size, OneBank increases available printed circuit board (PCB) real estate and drives down cost. Support is also retained for lane shifting, the jumperless autoconfiguration of peripheral boards.

What’s next for PC/104?

With the bandwidth boundaries of PCIe continuing to be pushed as hard as when it first landed, it’s unlikely any entirely new peripheral bus will replace PCIe any time soon. The third generation of PCIe, currently implemented in PC/104, offers a bandwidth of 8 Gbps, which is overkill for everything but the latest high-performance applications. The fourth generation will double this to 16 Gbps, though the development of interconnects is even further ahead, ready to support 28 Gbps.