Prototyping SoCs with customized PCI Express development boards

Using an FPGA board for ASIC prototyping can be helpful for SoC designers, yet it presents inherent challenges.

3Creating Small Form Factor (SFF) designs sometimes takes creating new devices, as this application story shows. To aid in developing a System-on-Chip (SoC), a small custom daughtercard held the key to integrating the right IP.

The ability to use an FPGA board for ASIC prototyping is a significant advantage for SoC designers, yet it often comes with inherent challenges. FPGA prototyping delivers a more accurate rendering of the finished ASIC by allowing designers to avoid time-intensive circuit emulation or extensive functional and gate-level simulation. Moreover, with the increase in FPGA densities, single FPGA prototyping boards offer obvious advantages over traditional multi-FPGA boards: space and power savings, elimination of the need for design partitioning, and easier and faster design integration and testing.

Real-world design challenge

In a recent design project, an SoC ASIC company was tasked with creating a custom chip for use in data storage applications. The end product needed to be as integrated and high performance as possible, both critical concerns in the data storage market.

To meet these needs, the design team sought out third-party IP to ensure a rock-solid, tested, and validated ASIC design. At the same time, the designers desired the ability to prototype FPGAs as a means of shrinking product testing and development cycles. The company struggled to find a solution that would provide:

  • The largest possible FPGA in a single FPGA board to avoid design partitioning in multiple FPGAs
  • A wide variety of interfaces including PCI Express 1.1 x1, two USB 2.0 Host/Device/On-The-Go (OTG) ports, DDR2 memory, one Ethernet 10/100/1000 port, and SPI flash
  • A carrier prototyping board that could be customized in 10 days and have the ability to integrate additional features
  • A product that would deliver the same IP in the ASIC product as it would in the FPGA prototype and as a result shrink the design cycle

Extending board capabilities

PLDA engineers took on this task using the PLDA XpressLX330T PCI Express development board, which had to be customized to include USB and additional SPI flash. The challenge was to accomplish this while maintaining compliance with the PCI Express Card Electromechanical Specification for add-on card width, length, and height. This compliance was necessary because the board was targeted for integration into tight, closed test systems with many other PCI Express boards in adjacent slots.

To address these requirements, the engineers decided to create a custom daughtercard – an SFF board that could extend the PCI Express carrier board's capabilities. Figure 1 shows a block diagram of the device. Features of the combined end product included:

Figure 1 | The XpressLX330T architecture includes USB, SPI flash, and PCI Express IP for extending the PCI Express carrier board's capabilities.

  • Two USB 2.0 Host/Device/OTG PHY ports (SMSC USB3300)
  • Three 1 Mb SPI flash interfaces (M25P10A)
  • An external power connector

– Power provided by USB Device when in Host mode

– Power provided by USB Host when in Device mode

  • A custom bracket with holes for USB micro-AB connectors
  • PLDA XpressRich2 PCI Express IP for use with FPGA prototyping and SoC design

– Mode used: x1, endpoint, Spec. 1.1 compliant

  • PLDA USB 3.0/2.0 Host/Device IP for use with FPGA prototyping and SoC design

Success in small spaces

In addition to consolidating several possible FPGAs into one board, the customized IP daughtercard (Figure 2) helped shrink the design cycle and allowed the SoC ASIC company to prototype FPGAs with the exact same IP and features that would be incorporated in its final product.

Figure 2 | A customized IP daughtercard can help shrink design cycles and enable FPGA prototyping.

By using a high-density single FPGA board for SoC prototyping, avoiding design partitioning in multiple FPGAs, and eliminating circuit emulation or extensive functional and gate-level simulation, the company successfully created an effective SoC ASIC for the integration-conscious data storage market.

Stephane Hauradou is CTO and cofounder of PLDA, based in Aix-en-Provence, France, with U.S. headquarters in San Jose, California. Stephane earned his Bachelor's degree in Engineering from the Polytechnic School of Montreal and his Master's degree in Microelectronics from Sup'Telecom in Paris. His thesis concentrated on the development of the first PCI IP controller for Programmable Logic Devices.