The role of innovation in the energy efficiency equation - Q&A with Benson Tao, VIA Technologies/S3 Graphics

3Leaps ahead in connected computing and low-power design are the basis for next-gen smart-energy apps. But these advances are dependent upon the industry's harnessing the latest innovations in manufacturing, software, and hardware - all to help to usher in the new revolution of green appliances.


SFF: What are the biggest challenges right now in designing embedded components for smart energy applications?

TAO: The current state of energy applications is still in its infancy, but the huge growth potential as multiple devices in every home need some form of connected intelligence make it a very attractive segment. Due to the early stage of adoption and multiple industry standards, many Machine-to-Machine (M2M) communications protocols exist for different in-home/out-of-home solutions. One challenge is the handshaking of different devices with seamless connectivity that plug-and-play and “talk” to each other with little or no intervention. As an example, device communications involves Wi-Fi, ZigBee, IEEE 802.15.4, 3G/4G, Ethernet, RF4CE, and others. To make matters more complicated, different countries have their own protocols, so multiple format support increases complexity and possible link failure points.

In addition, different system configurations and protocols increase software complexity for the Operating System (OS) and drivers due to multiple software stacks with some communications that may be proprietary and/or open. Proprietary and open standards have pros and cons related to development timelines and device connection handoffs.

Low power is another challenge as more devices go online. Because devices are always on to report, monitor, control, and adjust power metrics, they need to be power efficient.

Security is another key area that needs to be addressed, as a rogue hacker or unintentional compromise of the system can cause detrimental effects to the home or energy grid. The system needs to be looked at from both a software and hardware standpoint to be secure and robust and have failsafe mechanisms if compromised.

SFF: What technologies and design strategies is VIA using to overcome these challenges?

TAO: VIA has designed and acquired many fundamental IP blocks related to all aspects of computing and communications, from CPU, networking, peripheral, USB 3.0, display, and HD video components to cutting-edge 3D graphics. Through extensive customer designs and R&D initiatives, we have been building our knowledge base as we move forward with providing quality customer service.

Our approach has made us a value-add partner by helping customers understand intricate details of technologies and products. This allows them to get a complete solutions picture that includes hardware, software, manufacturing, and design methodologies. We also strive to understand our partners’ ecosystem to work with them to define an ideal solution since each design is unique.

To help overcome some of the issues of connectivity, software, power, and security, we create solutions that are simple and intuitive. Our platforms integrate common features into hardware for configurability and flexibility, and remain scalable to take advantage of different I/O and connections through multiple expansion ports. We also have a military-grade security engine called PadLock to help with secure energy appliance transactions.

Software customization and technology integration are part of our service team initiative. Expertise with OS and driver development can be leveraged across multiple technology teams under one umbrella for ease of support. This support also includes our ACE-CNX customization security service to utilize our PadLock engine.

Power is one of our fortes, and we architect products for high performance per watt and cycle efficiency.

SFF: Why are small form factors particularly useful in smart energy devices and systems?

TAO: Smart energy devices and systems can benefit from smaller form factors for reasons of portability, system placement, and flexibility, allowing a product to be used in a multitude of form factors ranging from a wall-mounted or tablet home control unit to an Internet-connected refrigerator system. As sizes shrink, designers’ creative juices start flowing, inspiring them to figure out how to get highly integrated, low-power products into fully functional, aesthetic, consumer-friendly devices with eye-catching GUIs. Smaller, better, and faster devices are attractive and can drive product strategies.

Another issue comes down to power dissi-pation of small form factors. Designers have less real estate to remove a given amount of heat without increasing the bill of materials cost for elaborate heat dissipation mechanisms. This creates an innovative avalanche spurred by demand, where system contributors – semiconductor suppliers, platform designers, foundries, and even software developers – continue thinking about cutting-edge ways to reduce power and heat.

As a pioneer in advancing x86 form factors that reduce power, area, and price, VIA has helped define some of the most well-known small form factors going back to the popular (Mini/Mobile/Pico/EM)-ITX (Figure 1). All of these modules enable feature-rich designs without sacrificing performance or increasing power. Continuing our trend of lighter, sleeker, power-efficient products, we participate in leading consortiums like SFF-SIG to define market-driven designs that balance features, I/O, and performance in a given power envelope.

Figure 1: VIA has helped define some of the most well-known small form factors going back to the popular (Mini/Mobile/Pico/EM)-ITX.

SFF: What technology advances are needed to further increase energy efficiency and promote green computing?

TAO: There are many pieces of the energy efficiency puzzle that need to come together to bring green computing to the next level. From the most fundamental standpoint comes the architecture and circuit design of the product, taking into account power modes and functional states, fine-grained power and clockgating of blocks and SRAMs, voltage levels and power planes, multicore with load balancing, gate usage efficiency, and other static and dynamic power reduction techniques. These approaches go along with the latest modeling, simulation, and circuit analysis tools needed for complex designs with thousands of nodes, multiple clock-tree structures, and other factors needed to optimize for power, area, throughput, and latency.

Process technology is yet another element. Variables from multi-VT designs and process technology characteristics go hand in hand with circuit and mixed-signal design. Advances below 40 nm/32 nm and semiconductor physics are key factors in lowering voltage and power based on the P=CV2F calculation.

The other components are package characteristics that affect power dispersion and system-level design, which includes power distribution efficiency, regulator design, and system thermals to regulate temperature and power.

Another major factor is the software design, which includes power management and control, event decision and response, running the OS and other interfaces, device management, performance modeling and feedback, along with code efficiency to minimize memory read/writes and unnecessary code execution or off-chip signaling that wastes energy.

From this discussion, there are many areas intertwined as part of the overall energy efficiency equation. Aggregate optimizations in each domain will effectively lower system power.

Benson Tao is senior product marketing manager at VIA/S3 Graphics, where he is responsible for product planning and business development. Benson has been in the GPU and video industry for the past 10 years, with roles as a system design engineer, FAE, and product manager for embedded graphics and video processors used in PCs, HDTVs, multimedia devices, and mission-critical server, medical, and military applications. He has worked for industry leaders like Trident Microsystems, Silicon Motion, and XGI.

VIA Technologies/S3 Graphics