What is PCI Express?

The PC/104 Embedded Consortium recently announced plans to release a variant of the PC/104 form factor that incorporates PCI Express serial bus architecture. The incorporation of PCI Express into the PC/104 form factor has tremendous potential for the future of the embedded system. This Fundamentals 101 column will study PCI bus limitations and the strengths of PCI Express.

The PC/104 Embedded Consortium recently announced plans to release a variant of the PC/104 form factor that incorporates PCI Express serial bus architecture. The incorporation of PCI Express into the PC/104 form factor has tremendous potential for the future of the embedded system. This Fundamentals 101 column will study PCI bus limitations and the strengths of PCI Express.

PCI bus limits
The PCI bus, which is incorporated on a PC/104-Plus form factor, is a 32-bit parallel bus interface running at 33 MHz with a maximum data throughput of 133 MBps. It is a mature, well-defined standard bus interface found in desktop systems and embedded systems. But, as technology progresses and system level requirements for data throughput continue to increase, PCI’s data rate limitations have become apparent. 

Certain types of data transmission with very high data bandwidth processing requirements such as advanced video processing and Gigabit Ethernet are already consuming a vast majority, if not exceeding, the entire bandwidth of the PCI bus. In addition, the PCI bus communication architecture is a shared parallel protocol and a complex interface for manipulating the proper data transfer across a shared bus topology. All devices connected to a PCI bus must share one common address and data bus, and must utilize an arbitration method for ownership of the bus to avoid bus contention between devices. The PCI bus also utilizes a multiplexed address/data bus architecture. The address and data bus both utilize the same physical wires that connect the PCI host to multiple devices, adding needless complexity.

PCI Express defined
PCI Express vastly differs from the standard PCI bus, which is a 32-bit unidirectional, shared bus medium. All peripherals connected to the PCI bus share the 133 MBps bandwidth of the bus and data that is passed in only one direction at a time along the bus between peripherals.

PCI Express is a high-performance, scalable, point-to-point, serial bus. PCI Express peripherals are connected through a link that consists of two pairs of Low Voltage Differential Signals (LVDS), one for data transmission and the other for receiving. These two pairs of wires, called a lane, allow full-duplex data transmission between devices. The clock signal is embedded within the serial data transfer using 8 B/10 B encoding, the same system utilized by Ethernet (100BASE-T, 100 Mbps) networks. This individual transmit/receive lane topology of the PCI Express architecture allows for a maximum transfer rate of 250 MBps in both directions simultaneously or an effective transfer rate of 500 MBps, nearly four times faster than PCI.

Multiple lanes can exist between two devices in a PCI Express architecture. Devices can have 1, 2, 4, 8, 16, or 32 lanes connected between them. Two PCI Express devices with 32 lanes connected between them can have a transfer rate of 8 GBps (32 * 250 MBps). Table 1 gives a comparative transfer rate of different bus architectures.

Bus Architecture

Max Transfer Rate

ISA

8 MBps

PCI

133 MBps

AGP 2x

533 MBps

AGP 4x

1,066 MBps

PCI Express x1

250 MBps

PCI Express x2

500 MBps

PCI Express x4

1,000 MBps

PCI Express x8

2,000 MBps

PCI Express x16

4,000 MBps

PCI Express x32

8,000 MBps

Table 1

Point-to-point communications
The PCI Express architecture is a point-to-point communication architecture. Each PCI device is directly connected to the host processor through a switched fabric topology interface similar to a router in a network (see Figure 1). As with data routing in a network, PCI Express data is packetized through the switched topology interface. This data packetization allows for data packet prioritization, thus granting continuous data streaming in applications such as video and audio.

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Figure 1: Each PCI device is directly connected to the host processor through a switched fabric topology interface similar to a router in a network