Thierry Wastiaux, Interface Concept
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FPGA coprocessors for acceleration of shape recognition algorithms in hybrid VPX HPEC systems
To reach the level of performance requested by the latest military specifications, electronic warfare (EW) systems designers rely more and more on VPX high-performance embedded computing (HPEC) platforms. To handle the global IP traffic growth - predicted to reach 132 exabytes (EB) per month in 2018, according to Cisco's Visual Network Index - electronic systems must manage the data flow in and out of the semiconductor devices. Designers of field-programmable gate arrays (FPGAs) have developed devices offering high bandwidth and performance with very high-speed interfaces that can bring superior parallel processing power. This reality enables the design of high-performance hybrid HPEC systems that can be used for such demanding applications as ultrafast shape-recognition systems.
